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Datasheet File OCR Text: |
preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. november 2010 doc id 17143 rev 2 1/108 1 stm32f101xf stm32f101xg xl-density access line, arm-bas ed 32-bit mcu with 768 kb to 1 mb flash, 15 timers, 1 ad c and 10 communication interfaces features core: arm 32-bit cortex?-m3 cpu with mpu ? 36 mhz maximum frequency, 1.25 dmips/mhz (dhrystone 2.1) performance ? single-cycle multiplication and hardware division memories ? 768 kbytes to 1 mbyte of flash memory (dual bank with read-w hile-write capability) ? 80 kbytes of sram ? flexible static memory controller with 4 chip select. supports compact flash, sram, psram, nor and nand memories ? lcd parallel interface, 8080/6800 modes clock, reset and supply management ? 2.0 to 3.6 v application supply and i/os ? por, pdr, and programmable voltage detector (pvd) ? 4-to-16 mhz crystal oscillator ? internal 8 mhz factory-trimmed rc ? internal 40 khz rc with calibration capability ? 32 khz oscillator for rtc with calibration low power ? sleep, stop and standby modes ?v bat supply for rtc and backup registers 1 x 12-bit, 1 s a/d converters (up to 16 channels) ? conversion range: 0 to 3.6 v ? temperature sensor 2 12-bit d/a converters dma ? 12-channel dma controller ? peripherals supported: timers, adc, dac, spis, i 2 cs and usarts up to 112 fast i/o ports ? 51/80/112 i/os, all mappable on 16 external interrupt vectors and almost all 5 v-tolerant debug mode ? serial wire debug (swd) & jtag interfaces ? cortex-m3 embedded trace macrocell? up to 15 timers ? up to ten 16-bit timers, with up to 4 ic/oc/pwm or pulse counters ? 2 watchdog timers (independent and window) ? systick timer: a 24-bit downcounter ? 2 16-bit basic timers to drive the dac up to 10 communication interfaces ? up to 2 x i 2 c interfaces (smbus/pmbus) ? up to 5 usarts (iso 7816 interface, lin, irda capability, modem control) ? up to 3 spis (18 mbit/s) crc calculation unit, 96-bit unique id ecopack ? packages table 1. device summary reference part number stm32f101xf stm32f101rf stm32f101vf stm32f101zf stm32f101xg STM32F101RG stm32f101vg stm32f101zg lqf p144 20 2 0 mm lqfp64 10 10 mm lqfp100 14 14 mm www.st.com
stm32f101xf, stm32f101xg 2/108 doc id 17143 rev 2 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 arm ? cortex?-m3 core with embedded flash and sram . . . . . . . . . 15 2.3.2 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.4 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 2.3.5 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.6 fsmc (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.7 lcd parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.8 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 16 2.3.9 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.10 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.11 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.12 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.15 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.16 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 rtc (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 19 2.3.18 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.20 universal synchronous/asynchronous receiver transmitters (usarts) 21 2.3.21 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.22 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.23 adc (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.24 dac (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.25 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.26 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.27 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 stm32f101xf, stm32f101xg doc id 17143 rev 2 3/108 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 38 5.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 38 5.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.7 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.10 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.12 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 78 5.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.16 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.17 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.18 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.19 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.3.20 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 stm32f101xf, stm32f101xg 4/108 doc id 17143 rev 2 6.2.2 evaluating the maximum junction temperature for an application . . . . 105 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 stm32f101xf, stm32f101xg doc id 17143 rev 2 5/108 table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f101xf and stm32f101xg features and peripheral counts . . . . . . . . . . . . . . . . . 11 table 3. stm32f101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. stm32f101xf and stm32f101xg timer feature comparison . . . . . . . . . . . . . . . . . . . . . . 19 table 5. stm32f101xf and stm32f101xg pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. fsmc pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 8. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 9. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 10. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 11. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 12. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 13. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 table 14. maximum current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 15. maximum current consumption in run mode, code with data processing running from ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 16. maximum current consumption in sleep mode, code running from flash or ram. . . . . . . 43 table 17. typical and maximum current consumptions in stop and standby modes . . . . . . . . . . . . 43 table 18. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 19. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 47 table 20. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 21. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 22. low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 23. hse 4-16 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 table 24. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 25. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 26. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 27. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 28. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 29. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 30. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 31. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . . 58 table 32. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . . 59 table 33. asynchronous multiplexed nor/psram read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 34. asynchronous multiplexed nor/psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 35. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 36. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 37. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 38. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 39. switching characteristics for pc card/cf read and write cycles . . . . . . . . . . . . . . . . . . . . 73 table 40. switching characteristics for nand flash read and write cycles . . . . . . . . . . . . . . . . . . . . 76 table 41. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 42. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 43. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 44. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 45. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 46. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 47. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 48. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 49. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 stm32f101xf, stm32f101xg 6/108 doc id 17143 rev 2 table 50. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 51. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 52. scl frequency (f pclk1 = 36 mhz, v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 53. stm32f10xxx spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 54. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 55. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 56. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 57. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 58. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 59. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 60. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 61. lqfp144, 20 x 20 mm, 144-pin thin quad flat package mechanical data . . . . . . . . . . . . 101 table 62. lqpf100 ? 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . 102 table 63. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package mechanical data . . . . . . . . 103 table 64. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 65. stm32f101xf and stm32f101xg ordering information scheme . . . . . . . . . . . . . . . . . . 106 stm32f101xf, stm32f101xg list of figures doc id 17143 rev 2 7/108 list of figures figure 1. stm32f101xf and stm32f101xg access line block diagram . . . . . . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. stm32f101xf and stm32f101xg access line lqfp144 pinout . . . . . . . . . . . . . . . . . . . 23 figure 4. stm32f101xf and stm32f101xg lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. stm32f101xf and stm32f101xg lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 7. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 8. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 9. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 10. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 11. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled. . . . . . . . . . . . . . . . . . 42 figure 12. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals disabled . . . . . . . . . . . . . . . . . 42 figure 13. typical current consumption on v bat with rtc on vs. temperature at different v bat values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 14. typical current consumption in stop mode with regulator in run mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 15. typical current consumption in stop mode with regulator in low-power mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 16. typical current consumption in standby mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 17. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 18. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 19. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 20. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 21. asynchronous non-multiplexed sram/psram/nor read waveforms . . . . . . . . . . . . . . . 58 figure 22. asynchronous non-multiplexed sram/psram/nor write waveforms . . . . . . . . . . . . . . . 59 figure 23. asynchronous multiplexed nor/psram read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 24. asynchronous multiplexed nor/psram write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 25. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 26. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 27. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 28. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 29. pc card/compactflash controller waveforms for common memory read access . . . . . . . 69 figure 30. pc card/compactflash controller waveforms for common memory write access . . . . . . . 70 figure 31. pc card/compactflash controlle r waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 32. pc card/compactflash controlle r waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 33. pc card/compactflash controller waveforms for i/o space read access . . . . . . . . . . . . . 72 figure 34. pc card/compactflash controller waveforms for i/o space write access . . . . . . . . . . . . . 73 figure 35. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 36. nand controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 37. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 75 figure 38. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 76 figure 39. standard i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 40. standard i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 list of figures stm32f101xf, stm32f101xg 8/108 doc id 17143 rev 2 figure 41. 5 v tolerant i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 42. 5 v tolerant i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 43. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 44. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 45. i 2 c bus ac waveforms and measurement circuit (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 46. spi timing diagram - slave mode and cpha=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 47. spi timing diagram - slave mode and cpha=1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 48. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 49. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 50. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 51. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 96 figure 52. power supply and reference decoupling (vref+ connected to vdda) . . . . . . . . . . . . . . . 97 figure 53. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 54. lqfp144, 20 x 20 mm, 144-pin thin quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 55. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 56. lqfp100 ? 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . 102 figure 57. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 58. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 103 figure 59. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 60. lqfp64 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 stm32f101xf, stm32f101xg introduction doc id 17143 rev 2 9/108 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f101xf and stm32f101xg xl-density access line microcontrollers. for more details on the whole stmicroelectronics stm32f101xx family, please refer to section 2.2: full compatibility throughout the family . the xl-density stm32f101xx datasheet should be read in conjunction with the stm32f10xxx reference manual. for information on programming, erasing and protection of the internal flash memory please refer to the stm32f10xxx flash programming manual. the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com. for information on the cortex?-m3 core please refer to the cortex?-m3 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. description stm32f101xf, stm32f101xg 10/108 doc id 17143 rev 2 2 description the stm32f101xf and stm32f101xg access line family incorporates the high- performance arm ? cortex?-m3 32-bit risc core operating at a 36 mhz frequency, high- speed embedded memories (flash memory up to 1 mbyte and sram of 80 kbytes), and an extensive range of enhanced i/os and peripherals connected to two apb buses. all devices offer one 12-bit adc, ten general-purpose 16-bit timers, as well as standard and advanced communication interfaces: up to two i 2 cs, three spis and five usarts. the stm32f101xx xl-density access line family operates in the ?40 to +85 c temperature range, from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. these features make the stm32f101xx xl-density access line microcontroller family suitable for a wide range of applications such as medical and handheld equipment, pc peripherals and gaming, gps platforms, industrial applications, plc, printers, scanners alarm systems , power meters, and video intercom. stm32f101xf, stm32f101xg description doc id 17143 rev 2 11/108 2.1 device overview the stm32f101xx xl-density access line family offers devices in 3 different package types: from 64 pins to 144 pins. depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. figure 1 shows the general block diagram of the device family. table 2. stm32f101xf and stm32f101xg features and peripheral counts peripherals stm32f101rx stm32f101vx stm32f101zx flash memory 768 kb 1 mb 768 kb 1 mb 768 kb 1 mb sram in kbytes 80 80 80 fsmc no yes yes timers general-purpose 10 basic 2 communication interfaces spi 3 i 2 c2 usart 5 gpios 51 80 112 12-bit adc number of channels 2 16 2 16 2 16 12-bit dac number of channels 2 2 cpu frequency 36 mhz operating voltage 2.0 to 3.6 v operating temperatures ambient temperature: ?40 to +85 c (see ta bl e 1 0 ) junction temperature: ?40 to +105 c (see ta b l e 1 0 ) package lqfp64 lqfp100 (1) 1. for the lqfp100 package, only fsmc bank1 an d bank2 are available. bank1 can only support a multiplexed nor/psram memory using the ne1 chip select. bank2 can only support a 16- or 8-bit nand flash memory using the nce2 chip select. the interr upt line cannot be used since port g is not available in this package. lqfp144 description stm32f101xf, stm32f101xg 12/108 doc id 17143 rev 2 figure 1. stm32f101xf and stm32f101xg access line block diagram 1. t a = ?40 c to +85 c (junction temperature up to 105 c). 2. af = alternate function on i/o port pin. pa[15:0] ext.it 112af ahb2 wkup f m a x : 3 6 mhz v ss i2c2 gp dma1 tim2 tim 3 xtal 3 2khz fl as h 512 k b yte v dd b a ck u p interf a ce tim4 b us m a trix 64 b it rtc rc 8 mhz cortex-m 3 cpu d bus o b l fl as h interf a ce u s art 2 s pi2 b a ck u p reg i2c1 rx, tx, ct s , r t s , u s art 3 rc 40 khz s t a nd b y iwdg @ v bat por / pdr @v dda v bat =1. 8 v to 3 .6 v ck, as af rx, tx , ct s , rt s , ck, as af nvic s pi1 interf a ce @v dda pvd int ahb2 apb2 awu s pi 3 uart4 rx,tx as af uart5 rx,tx as af tim5 pll @v dda f s mc dac_out1 as af dac_out2 as af s ram 8 0 k b yte gp dma2 tim6 tim7 njtr s t jtdi jtck/ s wclk jtm s / s wdio jtdo as af a[25:0] d[15:0] clk noe nwe ne[4:1] nbl[1:0] nwait nl as af 7 ch a nnel s 5 ch a nnel s gpio port a gpio port b gpio port c gpio port d gpio port e gpio port f gpio port g u s art1 temp. s en s or 12- b it adc if pb[15:0] pc[15:0] pd[15:0] pe[15:0] pf[15:0] pg[15:0] adc_in[0:15] @ v dda apb2: fm a x = 24/ 3 6 mhz apb1 tr a ce controller p bus i bus s y s tem re s et & clock control pclk1 pclk2 hclk fclk power volt. reg. 3 . 3 v to 1. 8 v su pply su pervi s ion @v dd por re s et nr s t v dda v ss a o s c_in o s c_out @v dd xtal o s c 4-16 mhz o s c 3 2_in o s c 3 2_out tamper-rtc/ alarm/ s econd out 4 ch a nnel s as af 4 ch a nnel s as af 4 ch a nnel s as af 4 ch a nnel s as af mo s i, mi s o s ck, n ss as af mo s i, mi s o s ck, n ss as af s cl, s da, s mba as af s cl, s da, s mba as af wwdg a i15 83 0 apb1: f m a x = 24/ 3 6 mhz traceclk traced[0: 3 ] as a s s w/jtag tpiu etm tr a ce/trig v ref+ v ref? v ref+ mo s i, mi s o, s ck, n ss as af rx, tx, ct s , rt s as af 12 b it dac1 if if if 12 b it dac 2 tim9 tim10 tim11 2 ch a nnel s as af 1 ch a nnel as af 1 ch a nnel as af tim12 tim1 3 tim14 2 ch a nnel s as af 1 ch a nnel as af 1 ch a nnel as af mpu fl as h 512 k b yte 64 b it o b l fl as h interf a ce stm32f101xf, stm32f101xg description doc id 17143 rev 2 13/108 figure 2. clock tree 1. when the hsi is used as a pll clock input, the maxi mum system clock frequency t hat can be achieved is 36 mhz. 2. to have an adc conversion time of 1 s, apb2 must be at 14 mhz or 28 mhz. ( 3 % / 3 # - ( z / 3 # ? ) . / 3 # ? / 5 4 / 3 # ? ) . / 3 # ? / 5 4 , 3 % / 3 # k ( z ( 3 ) 2 # - ( z , 3 ) 2 # k ( z t o i n d e p e n d e n t w a t c h d o g ) 7 $ ' 0 , , x x x 0 , , - 5 , ( 3 % ( i g h s p e e d e x t e r n a l c l o c k s i g n a l i g , 3 % , 3 ) ( 3 ) , e g e n d - # / # l o c k / u t p u t - a i n 0 , , 8 4 0 2 % x ! ( " 0 r e s c a l e r 0 , , # , + ( 3 ) ( 3 % ! 0 " 0 r e s c a l e r ! $ # 0 r e s c a l e r ! $ # # , + 0 # , + ( # , + 0 , , # , + t o ! ( " b u s c o r e m e m o r y a n d $ - ! t o ! $ # , 3 % , 3 ) ( 3 ) ( 3 ) ( 3 % p e r i p h e r a l s t o ! 0 " 0 e r i p h e r a l # l o c k % n a b l e % n a b l e 0 e r i p h e r a l # l o c k ! 0 " 0 r e s c a l e r 0 # , + t o ! 0 " p e r i p h e r a l s 0 e r i p h e r a l # l o c k % n a b l e - ( z m a x - ( z - ( z m a x - ( z m a x t o 2 4 # 0 , , 3 2 # 3 7 - # / # 3 3 t o # o r t e x 3 y s t e m t i m e r # l o c k % n a b l e 3 9 3 # , + m a x 2 4 # # , + 2 4 # 3 % , ; = 4 ) - x # , + ) 7 $ ' # , + 3 9 3 # , + & |